How to convert integer to std_logic_vector in vhdl?

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  1. Erin

    As LoneTech says, use ieee.numeric_std is your friend. You can convert a std_logic_vector to an integer, but you'll have to cast it as signed or unsigned first …
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  2. Black Teeth John

    VHDL BASIC Tutorial - Array, Memory, SRAM :

    how to convert integer to std_logic_vector in vhdl

    Ratings : 59 %   

      
  3. Falcon Thomas

    In reply to @Bhaumik: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SN74LS247 is Port ( BCD_I : in STD_LOGIC_VECTOR (3 downto 0); RBI : in STD_LOGIC;
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  4. Ray

    @Raphael : thanks for pointing out the mistake.I used xilinx ISE version 10.1. VHDL asserts are used to write intelligent testbenches. For these
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  5. Joey

    use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; conv_std_logic_vector(7, 9); converts integer 7 to a std_logic_vector with 9 bits. Rgds
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  6. Black Baron Charles

    Preliminary Remarks. This is a monthly posting to comp.lang.vhdl containing general information. Please send additional information directly to the editor:
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